A New Low Power 32×32-bit Multiplier

Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32×32-bit parallel multiplier, designed and fabricated using a 0.13 μm double-metal doublepoly CMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor logic circuits, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial-product generator and the partialproduct addition circuitry have been proposed, simulated and fabricated. An efficient radix-2 recoding logic generates the partial products. The multiplier supports 32×32-bit integer multiplication of both signed and unsigned operands. The multiplication time is 3.4 ns at a 1.3-V power supply. Our multiplication algorithm showed 7.4 percent speed improvement, 11 percent power savings and 9.5 percent reduction in transistor count when compared to the conventional multiplication algorithms.